1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to relatively thin sidewall spacers extending laterally from opposed sidewall surfaces of a transistor gate conductor.
2. Description of the Related Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing undoped polycrystalline silicon ("polysilicon") over a relatively thin gate oxide. The polysilicon material is then patterned to form a gate conductor directly above a channel region of the substrate. A dopant species is implanted into the gate conductor and regions of the substrate exclusive of the channel region, thereby forming source and drain regions adjacent to and on opposite sides of the channel region. If the dopant species used for forming the source and drain regions is n-type, then the resulting MOSFET is an NMOSFET ("n-channel") transistor device. Conversely, if the dopant species is p-type, then the resulting MOSFET is a PMOSFET ("p-channel") transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single substrate. While both types of devices can be formed, the devices are distinguishable based on the dopant species used.
While in operation, transistors which have heavily doped source and drain regions arranged laterally adjacent the gate conductor often experience a problem known as hot carrier injection ("HCI"). HCI is a phenomenon in which the kinetic energy of charged carriers (holes or electrons) within the channel region is increased as the carriers are accelerated through large potential gradients. As a result of this increase in kinetic energy, the charged carriers are injected into the gate oxide wherein they may become trapped. The greatest potential gradient, often referred to as the maximum electric field ("E.sub.m "), occurs near the drain during saturated operation. As a result of carrier entrapment within the gate oxide, a net negative charge density forms in the gate oxide. The trapped charge can accumulate with time, resulting in a positive threshold shift in an NMOS transistor, or a negative threshold shift in a PMOS transistor.
To overcome problems of sub-threshold current and threshold shift resulting from HCI, an alternative drain structure known as the lightly doped drain ("LDD") is commonly used. The purpose of the LDD is to absorb some of the potential into the drain and thus reduce E.sub.m. A conventional LDD structure is one in which a light concentration of dopant is self-aligned to the gate conductor followed by a heavier concentration of dopant self-aligned to the gate conductor on which a pair of sidewall spacers has been formed. The purpose of the first implant dose is to produce lightly doped sections within an active area of the substrate near the channel. The second implant dose is spaced from the channel by a distance substantially equivalent to the thickness of each sidewall spacer. The second implant dose forms heavily doped source and drain regions within the active area laterally outside the LDD areas. In this manner, the lateral thickness of each sidewall spacer dictates the length of each LDD area.
Unfortunately, the addition of LDD areas adjacent the channel adds parasitic resistance to the source-drain pathway, leading to many deleterious effects. For example, the parasitic resistance causes an increase in the value of the gate-to-source voltage, V.sub.GS, required for the drive current, I.sub.D, (i.e., current flowing between the source and drain regions of a transistor in its on-state) to reach saturation. Therefore, in order to reduce the parasitic resistance of the source-drain pathway, it has become necessary to reduce the lateral dimensions of the LDD areas. However, the length of each LDD area cannot be reduced below a specific dimension using conventional methods. In particular, the lateral thickness of the sidewall spacers used to define LDD areas generally has a limited minimum size. The sidewall spacers are typically formed by chemically-vapor depositing a layer of spacer material across the substrate and the gate conductor arranged above the substrate. The spacer material is thusly placed upon the opposed sidewall surfaces of the gate conductor, the upper surface of the gate conductor, and the upper surface of the substrate exterior to the gate conductor. The spacer material is then anisotropically etched such that it is removed from horizontally oriented surfaces faster than from vertically oriented surfaces. The duration of the anisotropic etch is preferably terminated after the spacer material has been removed from a significant portion of the horizontally oriented surfaces but before the spacer material can be completely removed from the vertically extending sidewall surfaces.
Although chemical-vapor deposition ("CVD") is not as vertically directed as physical vapor deposition, a CVD deposited material generally still tends to accumulate more quickly upon horizontally oriented surfaces than upon vertically oriented surfaces. In many instances, accumulation of the CVD deposited material is particularly poor upon tall vertical surfaces. As such, the thickness of a gate conductor, and hence the height of the sidewall surfaces which bound the gate conductor, must be maintained above, e.g., 200 .ANG., to ensure that the conductivity of the gate conductor is relatively high. While increasing the width of the gate conductor would also afford good conductivity of the gate conductor, it would undesirably lead to an increase in the threshold voltage, V.sub.T, of the transistor employing the gate conductor. Accordingly, in order to achieve good coverage of the vertically oriented sidewall surfaces of a necessarily thick gate conductor, an adequate amount of spacer material must be deposited across the gate conductor. Reducing the lateral thickness of the sidewall spacers thus cannot be achieved by decreasing the deposition time, and hence the thickness, of the spacer material. Moreover, the lateral thickness of the sidewall spacers cannot be reduced by increasing the anisotropic etch duration of the spacer material. That is, if the anisotropic etch is allowed to proceed too long, the gate conductor and the substrate will be over-etched, undesirably resulting in a significant decrease in the thicknesses of the gate conductor and the pre-existing LDD region within the substrate. In addition to preventing the reduction of the width of the LDD areas, this inability to reduce the lateral thickness of the spacers also limits the amount of packing density that can be achieved for an integrated circuit.
It would therefore be desirable to develop a method for fabricating a transistor having sidewall spacers of relatively small width. Since the lateral thickness of the sidewall spacers employed by a transistor determines the length of the LDDs, effectively controlling spacer thickness is important if parasitic resistance is to be decreased. Sidewall spacers having lateral dimensions reduced over the lateral thicknesses of spacers formed by conventional methods may be useful for producing smaller LDD regions and thus minimizing parasitic resistance in transistors having small lateral dimensions while effectively attenuating E.sub.m and minimizing HCI.